When scaling for next generation complementary metal-oxide semiconductor (CMOS) devices in connection with increased miniaturization, including, for example, very-large-scale integration (VLSI), middle-of-the-line (MOL) resistance can be a critical issue affecting device performance. Scaling of CMOS devices calls for independently reducing contact resistance of both n-type field-effect transistors (NFETs) and p-type field-effect transistors (PFETs), which requires different silicides for NFETs and PFETs, to independently achieve low contact resistance on both an NFET and a PFET, respectively.
Deposition of multiple liner silicides in a contact area trench can lead to unwanted extra liner deposition on contacts that results in a significant loss of available area in a trench for a gap fill metal contact and a subsequence increase in interconnect resistance.